1. Field of the Invention
This invention relates to integrated circuits in general, and more particularly to applications sensitive to device leakage currents and/or device gate oxide breakdown voltages.
2. Description of the Related Art
As power supply voltages are being reduced for reduced-dimension CMOS process technologies, leakage currents may become detrimental to circuit operation. For example, a standard NMOS device (e.g., an NMOS device having a minimum thickness oxide for a particular process technology) in 0.13 μm CMOS technology leaks approximately 1 nA through the gate oxide under at least one process corner and under some operating conditions. In addition, a circuit designed in a particular process technology may be coupled to a power supply (i.e., a node held at a constant voltage and providing variable current) having one of at least two different allowable voltage levels. In such a circuit, at the allowable levels of the power supply voltage, if the gate-to-source voltage of a device in the circuit exceeds an associated gate oxide breakdown voltage level, the circuit may not operate properly. Accordingly, improved techniques for implementing integrated circuits using reduced-dimension CMOS processes and integrated circuits responsive to multiple allowable power supply voltage levels are desired.